1 multimedia ics audio digital delay (karaoke echo) bu9252s / BU9252F the bu9252s and BU9252F are digital delays specifically for karaoke systems. each has an internal sample hold circuit, an 8-bit a / d and d / a converter and 2kb sram, and allows for the selection of one of eight delay times just by attaching an inexpensive ceramic resonator. a digital echo system can be formed by using either of these ics together with the ba7725s or ba7725fs. applications karaoke echo system electronic circuits that require signal delays features block diagram 1 s / h a in agnd a out av dd dcnt0 dcnt1 dcnt2 gnd v dd tst0 tst1 tst2 tdin tdo0 tdo1 osci osco s / h 8 2k sram address counter and main timing 8bit a / d 8bit d / a test circuit 2 3 5 4 6 7 8 9 18 17 16 15 14 13 12 11 10 1) internal digital delay circuit. 2) internal 8-bit a / d converter. sample rate. (14.22khz when f osc = 455khz). 3) internal 2k bytes data sram. 4) internal 8-bit d / a converter. 5) cmos design for low power consumption. 6) internal sample hold circuit. 7) internal feedback resistors and capacitors for oscilla- tor circuits.
2 multimedia ics bu9252s / BU9252F pin descriptions pin name 1 s / h 10 osco 2a in 11 osci 3 agnd 12 tdo1 4a out 13 tdo0 5av dd 14 tdin 6 dcnt0 15 tst2 7 dcnt1 16 tst1 8 dcnt2 17 tst0 9 gnd 18 v dd pin no. function pin no. pin name analog input analog output analog circuit power supply delay setting input delay setting input delay setting input function for attaching sample-and-hold capacitor analog circuit ground digital circuit ground test pin (output) test pin (output) test pin (input) test mode setting test mode setting test mode setting digital circuit power supply oscillator pin 1 oscillator pin 2
3 multimedia ics bu9252s / BU9252F input / output circuits pin name pin no. internal equivalent circuit pin name pin no. internal equivalent circuit s / h 1 osci osco 11 10 a in 2 tdin dcnt0 dcnt2 14 6 7 8 4 tdo0 tdo1 13 12 tst0 tst1 tst2 17 16 15 dcnt1 a out d / a + built-in 0.875x amplifier as output buffer.
4 multimedia ics bu9252s / BU9252F absolute maximum ratings (ta = 25?) parameter symbol limits unit power supply voltage v dd ?0.3 ~ + 7.0 v power dissipation mw storage temperature 55 ~ + 125 c input voltage v in 0.3 ~ v dd + 0.3 v output voltage v out ?0.3 ~ v dd + 0.3 v bu9252s BU9252F pd tstg 600 * 1 450 * 2 * 1 ic only. reduce by ?6mw / c for each in ta of 1 c over 25 c. * 2 ic only. reduce by 4.5mw / c for each in ta of 1 c over 25 c. recommended operating conditions parameter symbol limits unit v dd 4.5 ~ 5.5 v av dd v dd v v il 0.0 ~ 0.2v dd v v ih 0.8v dd ~ v dd v v ain 0 ~ av dd v f osc 200 ~ 1000 khz topr 10 ~ + 70 c power supply voltage analog power supply voltage input "l" voltage input "h" voltage analog input voltage clock frequency operating temperature electrical characteristics (unless otherwise noted, ta = 25?, v dd = av dd = 5v) parameter symbol min. typ. max. unit conditions i dd 3.5 12 ma i aout 14 ma 0.3 0.8 ma r ain 12 25 60 k w res 2 lsb v losc 0.6 1.2 v v hosc 3.8 4.4 v i oh = ?100 m a i osci 1620 m av osci = v dd 150 pf i ol = 100 m a v ain = av dd , f osc = 455khz v aout = 1v, v ain = 0v v aout = 0.5v dd , v ain = v dd * the bias circuit is impedance. * supply current analog output current analog input impedance a / d to d / a precision osco output "l" voltage osco output "h" voltage osci feedback loop current oscillation capacity
5 multimedia ics bu9252s / BU9252F circuit operation (1) external capacitor for signal input pin audio signals compressed by the ba7725s or ba7725fs have their dc component removed by an ac coupling capacitor and are then input to pin 2 of bu9252s or BU9252F. at this stage, level deviations occur because the input signal is capacitor-divided by this ac coupling capacitor c28 and by sampling hold capacitor c27 connected to pin 1. to prevent this, make sure that c27 is much lower than c28. (note: the numbers of external components are the numbers used in the sys- tem application example.) (3) delay timer settings the delay time (i.e., the length of time the signal is stored in the sram) can be set to any of eight settings between the maximum and minimum delay times by setting pins 6, 7 and 8 to the combination of logic sig- nal inputs that results in the corresponding number of counts. the maximum and minimum delay times are determined by the oscillation frequency of the attached ceramic resonator. 1 2 s / h c27 c28 the sample-held analog signal is converted to digital by the serial 8-bit a / d converter and then temporarily stored in the internal sram (2k bytes). (2) relationship between oscillation frequency (clk) and delay time sample rate f = f osc / 32 (fosc: oscillation frequency) f = 14.22khz at fosc = 455khz sample period t = 1 / f delay time dtime = t number of counts the delay time can be set to any of the eight settings shown below by setting the logic inputs of terminals dcnt0 through dcnt2. logic input count dcnt1 dcnt2 dcnt0 bu9252s / f 0 0 0 256 18.00 0 0 1 512 36.01 0 1 0 768 54.01 0 1 1 1024 72.02 1 0 0 1280 90.02 1 0 1 1536 108.03 1 1 0 1792 126.03 1 1 1 2048 144.04 bu9252s / f delay time (ms) (when f osc = 455khz) ccc (t) (db) c : delay time (ms)
6 multimedia ics bu9252s / BU9252F maximum and minimum delay times when using 300khz, 375khz and 455khz ceramic oscillators (4) peripheral components of the ceramic oscillator an oscillator circuit can be configured simply by attach- ing a 455khz ceramic resonator. 300khz 375khz 455khz max. min. max. min. max. min. 218.45 27.30 174.76 21.85 144.04 18.00 delay time (ms) rd rf osco osci external dimensions (units: mm) sop18 0.51min. 0 ~ 15 7.62 3.95 0.3 1.778 10 9 6.5 0.3 19.4 0.3 18 1 0.5 0.1 3.4 0.2 0.3 0.1 sdip18 BU9252F bu9252s 0.4 0.1 1.27 0.3min. 0.11 1.8 0.1 5.4 0.2 7.8 0.3 0.15 0.1 18 1 11.2 0.2 10 9 0.15
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